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74VHC595 8-Bit Shift Register with Output Latches
August 1993 Revised April 1999
74VHC595 8-Bit Shift Register with Output Latches
General Description
The VHC595 is an advanced high-speed CMOS Shift Register fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has eight 3-STATE outputs. Separate clocks are provided for both the shift register and the storage register. The shift register has a direct-overriding clear, serial input, and serial output (standard) pins for cascading. Both the shift register and storage register use positive-edge triggered clocks. If both clocks are connected together, the shift register state will always be one clock pulse ahead of the storage register. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages.
Features
s High Speed: tPD = 5.4 ns (typ) at VCC = 5V s Low power dissipation: ICC = 4 A (max) at TA = 25C s High noise immunity: VNIH = VNIL = 28% VCC (min) s Power down protection is provided on all inputs s Low noise: VOLP = 0.9V (typ) s Pin and function compatible with 74HC595
Ordering Code:
Order Number 74VHC595M 74VHC595SJ 74VHC595MTC 74VHC595N Package Number M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
(c) 1999 Fairchild Semiconductor Corporation
DS011640.prf
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74VHC595
Pin Descriptions
Pin Names SER SCK RCK SCLR G QA - QH Q'H Description Serial Data Input Shift Register Clock Input (Active rising edge) Storage Register Clock Input (Active rising edge) Reset Input 3-STATE Output Enable Input (Active LOW) Parallel Data Outputs Serial Data Output
Truth Table
Inputs Function SER RCK SCK SCLR G X X X X X X X X X X X L H QA thru QH 3-STATE L QA thru QH outputs enabled L Shift Register cleared QH = 0 L X H L Shift Register clocked QN = Qn-1, Q0 = SER = L H X H L Shift Register clocked QN = Qn-1, Q0 = SER = H X X H L Contents of Shift Register transferred to output latches
Timing Diagram
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Logic Diagram
(positive logic)
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Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Input Diode Current (IIK) Output Diode Current (IOK) DC Output Current (IOUT ) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) (Soldering, 10 seconds) 260C -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V -20 mA 20 mA 25 mA 75 mA -65C to +150C
Recommended Operating Conditions (Note 2)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC = 3.3V 0.3V VCC = 5.0V 0.5V 0 100 ns/V 0 20 ns/V 2.0V to +5.5V 0V to +5.5V 0V to VCC -40C to +85C
Note 1: Absolute Maximum Ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside databook specifications. Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
Symbol VIH VIL VOH Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage VCC (V) 2.0 3.0 - 5.5 2.0 3.0 - 5.5 2.0 3.0 4.5 3.0 4.5 VOL LOW Level Output Voltage 2.0 3.0 4.5 3.0 4.5 IOZ 3-STATE Output Off-State Current IIN ICC Input Leakage Current Quiescent Supply Current 0 - 5.5 5.5 0.1 4.0 1.0 40.0 A A VIN = 5.5V or GND VIN = VCC or GND 5.5 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.25 2.0 3.0 4.5 TA = 25C Min 1.50 0.7 VCC 0.50 0.3 VCC 1.9 2.9 4.4 2.48 3.80 0.1 0.1 0.1 0.44 0.44 2.5 A V IOL = 4 mA IOL = 8 mA VIN = VCC or GND VOUT = VCC or GND VING = VIH or VIL V V VIN = VIH or VIL IOH = -4 mA IOH = -8 mA IOL = 50 A V Typ Max TA = -40C to +85C Min 1.50 0.7 VCC 0.50 0.3 VCC Max Units V V VIN = VIH or VIL IOH = -50 A Conditions
Noise Characteristics
Symbol VOLP (Note 3) VOLV (Note 3) VIHD (Note 3) VILD (Note 3) Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage 5.0 1.5 5.0 3.5 5.0 -0.9 -1.2 VCC (V) 5.0 TA = 25C Typ 0.9 Limits 1.2 Units V V V V CL = 50 pF CL = 50 pF CL = 50 pF CL = 50 pF Conditions
Note 3: Parameter guaranteed by design.
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AC Electrical Characteristics
Symbol tPLH tPHL Parameter Propagation Delay Time RCK to QA-QH 5.0 0.5 tPLH tPHL Propagation Delay Time SCK-Q'H 5.0 0.5 tPHL Propagation Delay Time SCLR -Q'H 5.0 0.5 tPZL tPZH Output Enable Time G to QA-QH 5.0 0.5 tPLZ tPHZ fMAX Output Disable Time G to QA-QH Maximum Clock Frequency 5.0 0.5 tOSLH tOSHL CIN COUT CPD Output to Output Skew Input Capacitance Output Capacitance Power Dissipation Capacitance
Note 4: Parameter guaranteed by design. tOSLH = | tPLH max - tPLH min|; tOSHL = | tPHL max - tPHL min|. Note 5: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC.
VCC (V) 3.3 0.3
TA = +25C Min Typ 7.7 10.2 5.4 6.9 8.8 11.3 6.2 7.7 8.4 10.9 5.9 7.4 7.5 9.0 4.8 8.3 12.1 7.6 80 55 135 95 150 130 185 155 1.5 1.0 5.0 6.0 87 10 Max 11.9 15.4 7.4 9.4 13.0 16.5 8.2 10.2 12.8 16.3 8.0 10.0 11.5 15.0 8.6 10.6 15.7 10.3
TA = -40C to +85C Min 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 70 50 115 85 1.5 1.0 10 Max 13.5 17.0 8.5 10.5 15.0 18.5 9.4 11.4 13.7 17.2 9.1 11.1 13.5 17.0 10.0 12.0 16.2 11.0
Units ns ns ns ns ns ns ns ns ns MHz MHz ns pF pF pF
Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF RL = 1 k CL = 50 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF (Note 4) VCC = Open VCC = 5.0V (Note 5) CL = 50 pF CL = 50 pF
3.3 0.3
3.3 0.3
3.3 0.3
3.3 0.3 5.0 0.5 3.3 0.3
3.3 0.3 5.0 0.5
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74VHC595
AC Operating Requirements
Symbol tS tS tS tH tH tH tW(L) tW(L) tW(H) tW(L) tW(H) trem Parameter Minimum Setup Time (SER-SCK) Minimum Setup Time (SCK-RCK) Minimum Setup Time (SCLR -RCK) Minimum Hold Time (SER-SCK) Minimum Hold Time (SCK-RCK) Minimum Hold Time (SCLR -RCK) Minimum Pulse Width (SCLR) Minimum Pulse Width (SCK) Minimum Pulse Width (RCK) Minimum Removal Time (SCLR -SCK) VCC (V) 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 3.3 0.3 5.0 0.5 TA = 25C Typ 3.5 3.0 8.0 5.0 8.0 5.0 1.5 2.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 3.0 2.5 TA = -40C to +85C Guaranteed Minimum 3.5 3.0 8.5 5.0 9.0 5.0 1.5 2.0 0.0 0.0 0.0 0.0 5.0 5.0 5.0 5.0 5.0 5.0 3.0 2.5 Units ns ns ns ns ns ns
ns ns ns ns
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74VHC595
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74VHC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74VHC595 8-Bit Shift Register with Output Latches
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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